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JTAG-SMT2: Surface-mount Programming Module

$54.00
(4 reviews) Write a Review
SKU:
410-251

Note: Available in MSL3 level packaging. Please contact our sales department by submitting a form for purchasing information. 

This module is not needed for Digilent FPGA boards as our boards are designed with this functionality natively.

The joint test action group (JTAG)-SMT2 is a compact, complete and fully self-contained surface-mount programming module for Xilinx® field-programmable gate arrays (FPGAs). The module can be accessed directly from Xilinx tools, including iMPACT™, ChipScope™, and EDK. Users can load the module directly onto a target board and reflow it like any other component. 

The JTAG-SMT2 uses a 3.3V main power supply and a separate Vref supply to drive the JTAG signals. All JTAG signals use high speed, 24mA, three-state buffers that allow signal voltages from 1.8V to 5V and bus speeds of up to 30MBit/sec. The JTAG bus can be shared with other devices as systems hold JTAG signals at high-impedance, except when actively driven during programming. The SMT2 module is CE certified and fully compliant with EU RoHS and REACH directives. The module uses a standard Type-A to Micro-USB cable available for purchase from Digilent, Inc. 

Users can connect JTAG signals directly to the corresponding FPGA signals. For best results, mount the module adjacent to the edge of the host PCB over a ground plane. Although users may run signal traces on top of the host PCB beneath the SMT2, Digilent recommends keeping the area immediately beneath the SMT2 clear. Note: Keep the impedance between the SMT2 and FPGA below 100 Ohms to operate the JTAG at maximum speed. The SMT2 improves upon the SMT1 with the addition of three general purpose IO pins (GPIO0 – GPIO2) and support for interfacing IEEE 1149.7-2009 JTAG targets in both 2 and 4-wire modes.

  • Small, complete, all-in-one JTAG programming/debugging solution for Xilinx FPGAs
  • Compatible with Xilinx tools
  • Compatible with IEEE 1149.7-2009 Class T0 – Class T4 (includes 2-Wire JTAG)
  • GPIO pin allows debugging software to reset the processor core of Xilinx’s Zynq™ platform
  • Single 3.3V supply
  • Separate Vref drives JTAG signal voltages; Vref can be any voltage between 1.8V and 5V
  • High-Speed USB2 port that can drive JTAG/SPI bus at up to 30Mbit/sec (frequency settable by user)
  • SPI programming solution (modes 0 and 2 up to 30Mbit/sec, modes 1 and 3 up to 2Mbit/sec)
  • Uses micro-AB USB2 connector
  • Small form-factor surface-mount module can be directly loaded on target boards
  • A similar circuit is available as a stand-alone programming cable; see Digilent’s JTAG-HS2
  • Analog Devices ADP123AUJZ Linear Regulator
  • Fully supported by Digilent's Adept software and Adept SDK
  • Product Compliance: 
    • HTC: 8471801000
    • ECCN: EAR99
  • One JTAG-SMT2 programming module

Programming: Works with all Xilinx tools. Fully supported by Digilent's Adept software and Adept SDK

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4 Reviews Hide Reviews Show Reviews

  • 5
    Useful & Conveninet!

    Posted by purplrtl on 27th Jul 2021

    Added this module to some of my PCB designs to replace the clunky JTAG header. Works great and reliably! I can't seem to exceed 16 devices on the JTAG chain though. Simple fix was to just drop another one on my PCB.

  • 1
    expensive

    Posted by yunus on 20th Mar 2021

    too expensive for a such a useless thing

  • 5
    No problems, used with ISE and Spartan 3A FPGAs

    Posted by Erik on 14th Sep 2020

    I put this on a PCB as an integrated JTAG programmer. ISE/iMPACT recognized the connected devices immediately and programming and verification worked as expected. I used a Spartan 3A FPGA and Xilinx platform flash.

  • 1
    Interferes with Xilinx programming pod

    Posted by Digilent Customer on 26th Aug 2019

    Avnet Artix7A50T board. Both the Xilinx Platform Cable USB II and SmartLynq cables cannot program the QSPI flash on the board with Vivado 2018.2 Loading a BIT file works OK but the Digilent USB module is interfering with accessing the QSPI flash using Vivado and a Xilinx programming pod.